View ADV7125BCPZ170_6477146.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cmos, 330 mhz triple 8-bit high speed video dac adv7125 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2011 analog devices, inc. all rights reserved. features 330 msps throughput rate triple 8-bit dacs rs-343a-/rs-170-compatible output complementary outputs dac output current range: 2.0 ma to 26.5 ma ttl-compatible inputs internal reference (1.235 v) single-supply +5 v/+3.3 v operation 48-lead lqfp and lfcsp packages low power dissipation (30 mw minimum @ 3 v) low power standby mode (6 mw typical @ 3 v) industrial temperature range (?40c to +85c) pb-free (lead-free) packages qualified for automotive applications applications digital video systems high resolution color graphics digital radio modulation image processing instrumentation video signal reconstruction automotive infotainment units functional block diagram 8 8 8 8 8 8 data register dac dac blank sync r7 to r0 g7 to g0 b7 to b0 psave clock dac adv7125 data register data register blank and sync logic power-down mode voltage reference circuit ior ior iog iog iob v ref r set v aa comp gnd iob 03097-001 figure 1. general description the adv7125 (adv?) is a triple high speed, digital-to-analog converter on a single monolithic chip. it consists of three high speed, 8-bit video dacs with complementary outputs, a standard ttl input interface, and a high impedance, analog output current source. the adv7125 has three separate 8-bit-wide input ports. a single +5 v/+3.3 v power supply and clock are all that are required to make the part functional. the adv7125 has additional video control signals, composite sync and blank , as well as a power save mode. the adv7125 is fabricated in a 5 v cmos process. its monolithic cmos construction ensures greater functionality with lower power dissipation. the adv7125 is available in 48-lead lqfp and 48-lead lfcsp packages. product highlights 1. 330 msps (3.3 v only) throughput. 2. guaranteed monotonic to eight bits. 3. compatible with a wide variety of high resolution color graphics systems, including rs-343a and rs-170. adv is a registered trademar k of analog devices, inc.
adv7125 rev. c | page 2 of 16 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? 5 v electrical characteristics...................................................... 3 ? 3.3 v electrical characteristics................................................... 4 ? 5 v timing specifications ........................................................... 5 ? 3.3 v timing specifications ........................................................ 6 ? absolute maximum ratings............................................................ 7 ? esd caution.................................................................................. 7 ? pin configuration and function descriptions............................. 8 ? terminology .................................................................................... 10 ? circuit description and operation.............................................. 11 ? digital inputs .............................................................................. 11 ? clock input.................................................................................. 11 ? video synchronization and control........................................ 12 ? reference input........................................................................... 12 ? dacs ............................................................................................ 12 ? analog outputs .......................................................................... 12 ? gray scale operation................................................................. 13 ? video output buffers................................................................. 13 ? pcb layout considerations...................................................... 13 ? digital signal interconnect ....................................................... 13 ? analog signal interconnect....................................................... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 16 ? automotive products ................................................................. 16 ? revision history 2/11rev. b to rev. c change to table 6 ............................................................................. 8 7/10rev. a to rev. b change to features section ............................................................. 1 changes to clock frequency parameter, table 4 ......................... 6 changes to figure 2.......................................................................... 6 changes to figure 4 and figure 5................................................. 11 changes to table 7.......................................................................... 12 changes to endnotes to ordering guide .................................... 15 added automotive products section .......................................... 15 3/09rev. 0 to rev. a updated format..................................................................universal changes to features section, applications section, and general description section .......................................................................... 1 changes to figure 3 and table 6......................................................8 deleted ground planes section, power planes section, and supply decoupling section ........................................................... 11 changes to figure 5........................................................................ 11 changes to table 7, analog outputs section, figure 6, and figure 7 ............................................................................................ 12 changes to video output buffers section, pcb layout considerations section, and figure 9 .......................................... 13 changes to analog signal interconnect section and figure 10 .......................................................................................... 14 updated outline dimensions....................................................... 15 changes to ordering guide .......................................................... 16 10/02revision 0: initial version
adv7125 rev. c | page 3 of 16 specifications 5 v electrical characteristics v aa = 5 v 5%, v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 1 unless otherwise noted, t j max = 110c. table 1. parameter min typ max unit test conditions 1 static performance resolution (each dac) 8 bits integral nonlinearity (bsl) ?1 0.4 +1 lsb differential nonlinearity ?1 0.25 +1 lsb guaranteed monotonic digital and control inputs input high voltage, v ih 2 v input low voltage, v il 0.8 v input current, i in ?1 +1 a v in = 0.0 v or v dd psave pull-up current 20 a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high 2.0 18.5 ma rgb dac, sync = low dac-to-dac matching 1.0 5 % output compliance range, v oc 0 1.4 v output impedance, r out 100 k output capacitance, c out 10 pf i out = 0 ma offset error ?0.025 +0.025 % fsr tested with dac output = 0 v gain error 2 ?5.0 +5.0 % fsr fsr = 18.62 ma voltage reference, external and internal reference range, v ref 1.12 1.235 1.35 v power dissipation digital supply current 3 3.4 9 ma f clk = 50 mhz 10.5 15 ma f clk = 140 mhz 18 25 ma f clk = 240 mhz analog supply current 67 72 ma r set = 530 8 ma r set = 4933 standby supply current 4 2.1 5.0 ma psave = low, digital, and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% 1 temperature range t min to t max : ?40c to +85c at 50 mh z and 140 mhz, 0c to +70 c at 240 mhz and 330 mhz. 2 gain error = ((measured (fsc)/ideal (fsc) ? 1) 100), where ideal = v ref /r set k (0xffh) 4 and k = 7.9896. 3 digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 v and v dd . 4 these maximum/minimum specifications are guaranteed by characterization in the 4.75 v to 5.25 v range.
adv7125 rev. c | page 4 of 16 3.3 v electrical characteristics v aa = 3.0 v to 3.6 v, v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 1 unless otherwise noted, t j max = 110c. table 2. parameter 2 min typ max unit test conditions 1 static performance resolution (each dac) 8 bits r set = 680 integral nonlinearity (bsl) ?1 0.5 +1 lsb r set = 680 differential nonlinearity ?1 0.25 +1 lsb r set = 680 digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input current, i in ?1 +1 a v in = 0.0 v or v dd psave pull-up current 20 a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high 2.0 18.5 ma rgb dac, sync = low dac-to-dac matching 1.0 % output compliance range, v oc 0 1.4 v output impedance, r out 70 k output capacitance, c out 10 pf offset error 0 0 % fsr tested with dac output = 0 v gain error 3 0 % fsr fsr = 18.62 ma voltage reference, external reference range, v ref 1.12 1.235 1.35 v voltage reference, internal voltage reference, v ref 1.235 v power dissipation digital supply current 4 2.2 5.0 ma f clk = 50 mhz 6.5 12.0 ma f clk = 140 mhz 11 15 ma f clk = 240 mhz 16 ma f clk = 330 mhz analog supply current 67 72 ma r set = 560 8 ma r set = 4933 standby supply current 2.1 5.0 ma psave = low, digital, and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% 1 temperature range t min to t max : ?40c to +85c at 50 mh z and 140 mhz, 0c to +70 c at 240 mhz and 330 mhz. 2 these max/min specifications are guaranteed by characterization in the 3.0 v to 3.6 v range. 3 gain error = ((measure d (fsc)/ideal (fsc) ?1) 100), where ideal = v ref /r set k (0xffh) 4 and k = 7.9896. 4 digital supply is measured with continuous clock that has data in put corresponding to a ramp pattern and with an input level a t 0 v and v dd .
adv7125 rev. c | page 5 of 16 5 v timing specifications v aa = 5 v 5%, 1 v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 2 unless otherwise noted, t j max = 110c. table 3. parameter 3 symbol min typ max unit conditions analog outputs analog output delay t 6 5.5 ns analog output rise/fall time 4 t 7 1.0 ns analog output transition time 5 t 8 15 ns analog output skew 6 t 9 1 2 ns clock control clock frequency 7 f clk 0.5 50 mhz 50 mhz grade 0.5 140 mhz 140 mhz grade 0.5 240 mhz 240 mhz grade data and control setup 6 t 1 0.5 ns data and control hold 6 t 2 1.5 ns clock period t 3 4.17 ns clock pulse width high 6 t 4 1.875 ns f clk_max = 240 mhz clock pulse width low 6 t 5 1.875 ns f clk_max = 240 mhz clock pulse width high 6 t 4 2.85 ns f clk_max = 140 mhz clock pulse width low 6 t 5 2.85 ns f clk_max = 140 mhz clock pulse width high t 4 8.0 ns f clk_max = 50 mhz clock pulse width low t 5 8.0 ns f clk_max = 50 mhz pipeline delay 6 t pd 1.0 1.0 1.0 clock cycles psave up time 6 t 10 2 10 ns 1 the maximum and minimum specifications are guaranteed over this range. 2 temperature range t min to t max : ?40c to +85c at 50 mhz and 140 mhz, 0c to +70c at 240 mhz. 3 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) for both 5 v and 3.3 v supplies. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a fu ll-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk maximum specification production tested at 125 mhz and 5 v. limits specified here are guar anteed by characterization.
adv7125 rev. c | page 6 of 16 3.3 v timing specifications v aa = 3.0 v to 3.6 v, 1 v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 2 unless otherwise noted, t j max = 110c. table 4. parameter 3 symbol min typ max unit conditions analog outputs analog output delay, t 6 7.5 ns analog output rise/fall time 4 t 7 1.0 ns analog output transition time 5 t 8 15 ns analog output skew 6 t 9 1 2 ns clock control clock frequency 7 f clk 50 mhz 50 mhz grade 140 mhz 140 mhz grade 240 mhz 240 mhz grade 330 mhz 330 mhz grade data and control setup 6 t 1 0.2 ns data and control hold 6 t 2 1.5 ns clock period t 3 3 ns clock pulse width high 6 t 4 1.4 ns f clk_max = 330 mhz clock pulse width low 6 t 5 1.4 ns f clk_max = 330 mhz clock pulse width high 6 t 4 1.875 ns f clk_max = 240 mhz clock pulse width low 6 t 5 1.875 ns f clk_max = 240 mhz clock pulse width high 6 t 4 2.85 ns f clk_max = 140 mhz clock pulse width low 6 t 5 2.85 ns f clk_max = 140 mhz clock pulse width high t 4 8.0 ns f clk_max = 50 mhz clock pulse width low t 5 8.0 ns f clk_max = 50 mhz pipeline delay 6 t pd 1.0 1.0 1.0 clock cycles psave up time 6 t 10 4 10 ns 1 these maximum and minimum specificatio ns are guaranteed over this range. 2 temperature range: t min to t max : ?40c to +85c at 50 mh z and 140 mhz, 0c to +70 c at 240 mhz and 330 mhz. 3 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) for 3.3 v supplies. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a fu ll-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk maximum specification production tested at 125 mhz and 5 v. limits specified here are guar anteed by characterization. t 3 t 1 t 4 t 8 t 2 t 6 t 7 t 5 clock digital inputs (r7 to r0, g7 to g0, b7 to b0, sync, blank) analog outputs (ior, ior, iog, iog, iob, iob) notes 1. output delay ( t 6 ) measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 2. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full-scale transition. 3. transition time ( t 8 ) measured from the 50% point of full-scale transition to within 2% of the final output value. 03097-002 figure 2. timing diagram
adv7125 rev. c | page 7 of 16 absolute maximum ratings table 5. parameter rating v aa to gnd 7 v voltage on any digital pin gnd ? 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) ?40c to +85c storage temperature (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec) 300c vapor phase soldering (1 minute) 220c i out to gnd 1 0 v to v aa 1 analog output short circuit to any power supply or common gnd can be of an indefinite duration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adv7125 rev. c | page 8 of 16 pin configuration and fu nction descriptions 13 14 15 16 17 18 19 20 21 22 23 24 v aa gnd gnd b0 b1 b2 b3 b4 b5 b6 b7 clock 48 47 46 45 44 43 42 41 40 39 38 37 r7 r6 r5 r4 r3 r2 r1 r0 gnd gnd psave r set 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd g0 g1 g2 g3 g4 g5 g6 g7 blan k sync notes 1. the lfcsp_vq has an exposed paddle that must be connected to gnd. comp v aa v aa iob iob gnd gnd 35 v ref 36 34 33 32 31 30 29 28 27 26 25 top view (not to scale) adv7125 pin 1 indicator 03097-003 iog iog ior ior figure 3. pin configuration table 6. pin function descriptions pin nuber neonic description 1, 2, 14, 15, 25, 26, 39, 40 gnd ground. all gnd pins must be connected. 3 to 10, 16 to 23, 41 to 48 g0 to g7, b0 to b7, r0 to r7 red, green, and blue pixel data inputs (ttl compatib le). pixel data is latched on the rising edge of clock. r0, g0, and b0 are the least significant da ta bits. unused pixel data inputs should be connected to either the regular printed circuit board (pcb) power or ground plane. 11 blank composite blank control input (ttl compatible). a logic 0 on this control input drives the analog outputs, ior, iob, and iog, to the blanking level. the blank signal is latched on the rising edge of clock. while blank is a logic 0, the r0 to r7, g0 to g7, and b0 to b7 pixel inputs are ignored. 12 sync composite sync control input (ttl compatible). a logic 0 on the sync input switches off a 40 ire current source. this is internally connected to the iog analog output. sync does not override any other control or data input; therefore, it shou ld only be asserted during the blanking interval. sync is latched on the rising edge of clock. if sync information is not required on the green channel, the sync input should be tied to logic 0. 13, 29, 30 v aa analog power supply (5 v 5%). all v aa pins on the adv7125 must be connected. 24 clock clock input (ttl compatible). the rising edge of clock latches the r0 to r7, g0 to g7, b0 to b7, sync , and blank pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. 33, 31, 27 ior , iog , iob differential red, green, and blue current outputs (high impedance current sources). these rgb video outputs are specified to directly drive rs-343a and rs-170 video levels into a doubly terminated 75 load. if the complementary outputs are not requir ed, these outputs should be tied to ground. 34, 32, 28 ior, iog, iob red, green, and blue current outputs. these high impedance current sources are capable of directly driving a doubly terminated 75 coaxial cable. a ll three current outputs should have similar output loads whether or not they are all being used. 35 comp compensation pin. this is a compensation pin for the internal reference amplifier. a 0.1 f ceramic capacitor must be connected between comp and v aa . 36 v ref voltage reference input for dacs or voltage reference output (1.235 v).
adv7125 rev. c | page 9 of 16 pin number mnemonic description 37 r set a resistor (r set ) connected between this pin and gnd controls the magnitude of the full-scale video signal. note that the ire relationships are maintain ed, regardless of the full-scale output current. the relationship between r set and the full-scale output current on iog (assuming i sync is connected to iog) is given by: r set () = 11,445 v ref (v)/ iog (ma) the relationship between r set and the full-scale output current on ior, iog, and iob is given by: iog (ma) = 11,444.8 v ref (v)/ r set () ( sync being asserted) ior , iob (ma) = 7989.6 v ref (v)/ r set () the equation for iog is the same as that for ior and iob when sync is not being used, that is, sync tied permanently low. 38 psave power save control pin. reduced power consumptio n is available on the adv7125 when this pin is active. 49 (epad) ep (epad) the lfcsp_vq has an expo sed paddle that must be connected to gnd.
adv7125 rev. c | page 10 of 16 terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level that shuts off the picture tube, resulting in the blackest possible picture. color video (rgb) this refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. sync signal ( sync ) the position of the composite video signal that synchronizes the scanning process. gray scale the discrete levels of video signal between reference black and reference white levels. an 8-bit dac contains 256 different levels. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. sync level the peak level of the sync signal. video signal the portion of the composite video signal that varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion that can be visually observed.
adv7125 rev. c | page 11 of 16 circuit description and operation the adv7125 contains three 8-bit dacs, with three input channels, each containing an 8-bit register. also integrated on board the part is a reference amplifier. the crt control functions, blank and sync , are integrated on board the adv7125. digital inputs there are 24 bits of pixel data (color information), r0 to r7, g0 to g7, and b0 to b7, latched into the device on the rising edge of each clock cycle. this data is presented to the three 8-bit dacs and then converted to three analog (rgb) output wave- forms (see figure 4 ). clock data digital inputs (r7 to r0, g7 to g0, b7 to b0, sync, blank) analog outputs (ior, ior, iog, iog, iob, iob) 03097-004 figure 4. video data input/output the adv7125 has two additional control signals that are latched to the analog video outputs in a similar fashion. blank and sync are each latched on the rising edge of clock to maintain synchronization with the pixel data stream. the blank and sync functions allow for the encoding of these video synchronization signals onto the rgb video output. this is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the blank and sync digital inputs. figure 5 shows the analog output, rgb video waveform of the adv7125. the influence of sync and blank on the analog video waveform is illustrated. table 7 details the resultant effect on the analog outputs of blank and sync . all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the adv7125 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and thus the required clock frequency, is determined by the on-screen resolution, according to the following equation: dot rate = ( horiz res ) (vert res) (refresh rate )/( retrace factor ) where: horiz res is the number of pixels per line. ver t res is the number of lines per frame. refresh rate is the horizontal scan rate. this is the rate at which the screen must be refreshed, typically 60 hz for a noninterlaced system, or 30 hz for an interlaced system. retrace factor is the total blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (for example, 0.8). therefore, for a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate, and a retrace factor of 0.8, dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the adv7125 on the rising edge of clock, as previously described in the digital inputs section. it is recommended that the clock input to the adv7125 be driven by a ttl buffer (for example, the 74f244). red and blue notes 1. outputs connected to a doubly terminated 75 ? load. 2 . v ref = 1.235v, r set = 530 ? . 3 . rs-343 levels and tolerances assumed on all levels. ma v 18.67 0.7 00 ma v 26.0 0.975 white level blank level sync level 7.2 0.271 00 green 03097-005 figure 5. typical rgb video output waveform
adv7125 rev. c | page 12 of 16 table 7. typical video output truth table (r set = 530 , r load = 37.5 ) video output level iog (ma) iog (ma) ior/iob (ma) ior / iob (ma) sync blank dac input data white level 26.0 0 18.67 0 1 1 0xffh video video + 7.2 18.67 ? video video 18.67 ? video 1 1 data video to blank video 18.67 ? video video 18.67 ? video 0 1 data black level 7.2 18.67 0 18.67 1 1 0x00h black to blank 0 18.67 0 18.67 0 1 0x00h blank level 7.2 18.67 0 18.67 1 0 0xxxh (dont care) sync level 0 18.67 0 18.67 0 0 0xxxh (dont care) video synchronization and control the adv7125 has a single composite sync ( sync ) input control. many graphics processors and crt controllers have the ability to generate horizontal sync (hsync), vertical sync (vsync), and composite sync . in a graphics system that does not automatically generate a composite sync signal, the inclusion of some additional logic circuitry enables the generation of a composite sync signal. the sync current is internally connected directly to the iog output, thus encoding video synchronization information onto the green video channel. if it is not required to encode sync information onto the adv7125, the sync input should be tied to logic low. reference input the adv7125 contains an on-board voltage reference. the v ref pin should be connected as shown in figure 10 . a resistance, r set , connected between the r set pin and gnd, determines the amplitude of the output video level according to equation 1 and equation 2 for the adv7125. iog (ma) = 11,444.8 v ref ( v )/ r set () (1) ior , iob (ma) = 7989.6 v ref (v)/ r set () (2) equation 1 applies to the adv7125 only, when sync is being used. if sync is not being encoded onto the green channel, equation 1 is similar to equation 2. using a variable value of r set allows for accurate adjustment of the analog output video levels. use of a fixed 560 r set resistor yields the analog output levels quoted in the specifications section. these values typically correspond to the rs-343a video wave- form values, as shown in figure 5 . dacs the adv7125 contains three matched 8-bit dacs. the dacs are designed using an advanced, high speed, segmented architec- ture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. because all this circuitry is on one monolithic device, matching between the three dacs is optimized. as well as matching, the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. the on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. analog outputs the adv7125 has three analog outputs, corresponding to the red, green, and blue video signals. the red, green, and blue analog outputs of the adv7125 are high impedance current sources. each one of these three rgb current outputs is capable of directly driving a 37.5 load, such as a doubly terminated 75 coaxial cable. figure 6 shows the required configuration for each of the three rgb outputs connected into a doubly terminated 75 load. this arrangement develops rs-343a video output voltage levels across a 75 monitor. a suggested method of driving rs-170 video levels into a 75 monitor is shown in figure 7 . the output current levels of the dacs remain unchanged, but the source termination resistance, z s , on each of the three dacs is increased from 75 to 150 . ior, iog, iob z s = 75 ? (source termination) termination repeated three times for red, green, and blue dacs z l = 75 ? (monitor) z 0 = 75 ? (cable) dacs 03097-006 figure 6. analog output termination for rs-343a ior, iog, iob z s = 150 ? (source termination) termination repeated three times for red, green, and blue dacs z l = 75 ? (monitor) z 0 = 75 ? (cable) dacs 03097-007 figure 7. analog output termination for rs-170 more detailed information regarding load terminations for various output configurations, including rs-343a and rs-170, is available in the an-205 application note, video formats and required load terminations , available from analog devices at www.analog.com .
adv7125 rev. c | page 13 of 16 figure 5 shows the video waveforms associated with the three rgb outputs driving the doubly terminated 75 load of figure 6 . as well as the gray scale levels (black level to white level), figure 5 also shows the contributions of sync and blank for the adv7125. these control inputs add appro- priately weighted currents to the analog outputs, producing the specific output level requirements for video applications. details how the table 7 sync and blank inputs modify the output levels. gray scale operation the adv7125 can be used for standalone, gray scale (mono- chrome) or composite video applications (that is, only one channel used for video information). any one of the three channels, red, green, or blue, can be used to input the digital video data. the two unused video data channels should be tied to logic 0. the unused analog outputs should be terminated with the same load as that for the used channel, that is, if the red channel is used and ior is terminated with a doubly terminated 75 load (37.5 ), iob and iog should be terminated with 37.5 resistors (see figure 8 ). r0 r7 g0 adv7125 g7 b0 b7 ior iog 37.5 ? doubly terminated 75 ? load video output 37.5 ? iob gnd 03097-008 figure 8. input and output connections for standalone gray scale or composite video video output buffers the adv7125 is specified to drive transmission line loads. the analog output configuration to drive such loads is described in the analog outputs section and illustrated in figure 9 . however, in some applications, it may be required to drive long transmis- sion line cable lengths. cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. the inclusion of output buffers compensates for some cable distortion. buffers with large full power bandwidths and gains between two and four are required. these buffers also need to be able to supply sufficient current over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad843, ad844, ad847, and ad848 series of monolithic op amps. in very high frequency applications (80 mhz), the ad8061 is recommended. more information on line driver buffering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit results in any desired video level. 3 7 2 z l = 75 ? (monitor) z 0 = 75 ? z 2 z 1 +v s ?v s 0.1f 0.1f 75 ? (cable) gain (g) = 1 + dacs ior, iog, iob z s = 75 ? (source termination) ad848 4 6 03097-009 z 1 z 2 figure 9. ad848 as an output buffer pcb layout considerations the adv7125 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the adv7125, it is imperative that great care be given to the pcb layout. figure 10 shows a recommended connection diagram for the adv7125. the layout should be optimized for lowest noise on the adv7125 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. shorten the lead length between groups of v aa and gnd pins to minimize inductive ringing. it is recommended to use a 4-layer printed circuit board with a single ground plane. the ground and power planes should separate the signal trace layer and the solder side layer. noise on the analog power plane can be further reduced by using multiple decoupling capacitors (see figure 10 ). optimum performance is achieved by using 0.1 f and 0.01 f ceramic capacitors. individually decouple each v aa pin to ground by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. it is important to note that while the adv7125 contains circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, pay close attention to reducing power supply noise. a dc power supply filter (murata bnx002) provides emi suppression between the switching power supply and the main pcb. alternatively, consideration can be given to using a 3- terminal voltage regulator. digital signal interconnect isolate the digital signal lines to the adv7125 as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the adv7125 should be avoided to minimize noise pickup. connect any active pull-up termination resistors for the digital inputs to the regular pcb power plane (v cc ) and not to the analog power plane.
adv7125 rev. c | page 14 of 16 analog signal interconnect for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 (doubly terminated 75 configuration). this termination resistance should be as close as possible to the adv7125 to minimize reflections. place the adv7125 as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high frequency power supply rejection. additional information on pcb design is available in the an-333 application note, design and layout of a video graphics system for reduced emi , which is available from analog devices at www.analog.com . 35 36 37 33 31 27 r7 to r0 41 to 48 comp v aa v aa v aa v aa v ref r set ior 75? 75? 75? coaxial cable 75? power supply decouplin g (0.1f and 0.01f capacitor for each v aa group ) ad1580 adv7125 monitor (crt) 1 2 bnc connectors complementary outputs 75? 1k? r set 530? iog iob 12 sync 11 blank 24 clock 38 psave gnd 1, 2, 14, 15, 25, 26, 39, 40 13, 29, 30 video data inputs g7 to g0 3to 10 b7 to b0 16 to 23 ior iog iob 75? 75? 32 28 34 0.1f 0.1f 1f 0.01f 03097-010 figure 10. typical connection diagram
adv7125 rev. c | page 15 of 16 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 11. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 12. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters
adv7125 rev. c | page 16 of 16 ordering guide model 1 , 2 , 3 temperature range package description speed option package option adv7125kstz50 ?40c to +85c 48-lead lqfp 50 mhz st-48 adv7125kstz50-reel ?40c to +85c 48-lead lqfp 50 mhz st-48 adv7125kstz140 ?40c to +85c 48-lead lqfp 140 mhz st-48 adv7125jstz240 0c to +70c 48-lead lqfp 240 mhz st-48 adv7125jstz330 0c to +70c 48-lead lqfp 330 mhz st-48 adv7125wbstz170 ?40c to +85c 48-lead lqfp 170 mhz st-48 adv7125wbstz170-rl ?40c to +85c 48-lead lqfp 170 mhz st-48 ADV7125BCPZ170 ?40c to +85c 48-lead lfcsp_vq 170 mhz cp-48-1 ADV7125BCPZ170-rl ?40c to +85c 48-lead lfcsp_vq 170 mhz cp-48-1 adv7125wbcpz170 ?40c to +85c 48-lead lfcsp_vq 170 mhz cp-48-1 adv7125wbcpz170-rl ?40c to +85c 48-lead lfcsp_vq 170 mhz cp-48-1 1 z = rohs compliant part. 2 w = qualified for auto motive applications. 3 adv7125jstz330 is available in a 3.3 v option only. automotive products the adv7125w models are available with controlled manufacturing to support the quality and reliability requirements of automoti ve applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. ?2002C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03097-0-2/11(c)

▲Up To Search▲

Price & Availability of ADV7125BCPZ170

	To Download ADV7125BCPZ170 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .